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Memory Segmentation and Paging
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Memory Segmentation and Paging
Memory Segmentation and Paging
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1
Question
What is a Logical address and a Virtual address?
Answer
Logical addresses are used by an application program and consist of a 16-bit selector and a 32-bit offset. Virtual addresses are the same as logical addresses, used by user mode in the operating system and mapped from logical addresses.
2
Question
What is a Linear address and a Physical address?
Answer
Linear addresses are calculated from virtual/logical addresses by segment translation (segmentation). When paging is disabled, linear address = physical address. Physical addresses appear on the pins of the processor during memory read/write operations and are calculated from linear addresses through paging.
3
Question
Explain the Segment Translation Process.
Answer
Segment Translation is a process of converting logical address into a linear address. The processor uses descriptors, descriptor tables, selectors, and segment registers to perform this translation.
4
Question
What is the purpose of a Segment Descriptor?
Answer
The segment descriptor provides the processor with the data it needs to map a logical address into a linear address.
5
Question
Define the following descriptor fields: BASE TYPE DPL LIMIT Granularity bit(G) AVL/U(User bit) Segment-Present bit(P) Accessed bit(A)
Answer
BASE: Defines the location of the segment within the 4 gigabyte linear address space. TYPE: Distinguishes between various kinds of descriptors. DPL (Descriptor Privilege Level): Used by the protection mechanism LIMIT: Defines the size of the segment. Granularity bit(G): Specifies the units with which the LIMIT field is interpreted. AVL/U(User bit): This bit is completely undefined, and 80386 ignores it.(available for user or OS) Segment-Present bit(P): If this bit is zero, the descriptor is not valid for use in address transformation; the processor will signal an exception when a selector for the descriptor is loaded into a segment register Operating systems that implement segment-based virtual memory clear the present bit. Accessed bit(A): The processor sets this bit when the segment is accessed.
6
Question
What are Descriptor Tables?
Answer
Descriptor tables are a group of segment descriptors placed in a continuous memory location. Each descriptor requires 8 bytes. Max length(Size) =64KB. There are 3 types of descriptor tables: GDT, LDT and IDT.
7
Question
What are the Global Descriptor Table (GDT) and Local Descriptor Table (LDT)?
Answer
The Global Descriptor Table (GDT) is a general-purpose table of descriptors used by all programs to reference segments of memory. The Local Descriptor Table (LDT) is set up in the system for individual tasks or closely related groups of tasks.
8
Question
What is a Local Descriptor Table (LDT) and what is its function?
Answer
Each task can have its own LDT or share it with others. It defines a local memory address space for the task and contains descriptors for code and data segments.
9
Question
What is the purpose of the Table Indicator (TI) in a selector?
Answer
The Table Indicator (TI) specifies which descriptor table a selector refers to. A zero indicates the GDT, and a one indicates the current LDT.
10
Question
List the three types of descriptors held by Interrupt Descriptor Table (IDT)
Answer
Trap Gate Descriptor, Interrupt Gate Descriptor, and Task Gate Descriptor
11
Question
What is the default value that loads into Interrupt Descriptor Table Register (IDTR)?
Answer
Base Address = 0, Limit = 03FFH
12
Question
What is the Global Descriptor Table Register (GDTR) and its components?
Answer
The Global Descriptor Table Register (GDTR) is a 48-bit register that points to the GDT, containing a 32-bit base address and a 16-bit limit.
13
Question
How is the size of the GDT determined from the LIMIT field in the GDTR?
Answer
The limit value is 1 less than the actual size of the table. For example, if the limit is 03FFH, the table is 1024 bytes long.
14
Question
What information is stored in the Local Descriptor Table Register?
Answer
The Local Descriptor Table Register holds the 32-bit base address, 16-bit segment limit, and 16-bit segment selector for the LDT. It also has a 48-bit cache register.
15
Question
How do GDT and LDT relate to descriptors of each other?
Answer
The GDT contains LDT descriptors, but there is no segment descriptor for the GDT itself.
16
Question
What is the Interrupt Descriptor Table Register (IDTR) and its components?
Answer
The Interrupt Descriptor Table Register (IDTR) is a 48-bit register that points to the IDT, containing a 32-bit base address and a 16-bit limit. It is used by interrupts and exceptions only.
17
Question
Name the three fields of a Selector
Answer
Index, Table Indicator (TI), and Requested Privilege Level (RPL)
18
Question
How does the processor use the index value in a selector to access a descriptor in a descriptor table?
Answer
The processor multiplies the index value by 8 (the length of a descriptor) and adds the result to the base address of the descriptor table.
19
Question
What is the role of segment registers in memory access?
Answer
Segment registers store information from descriptors, avoiding the need to consult descriptor tables for every memory access. They have visible and invisible portions.
20
Question
What are the two classes of instructions used to load segment registers?
Answer
Direct load instructions (e.g., MOV, POP) and implied load instructions (e.g., far CALL, JMP).
21
Question
What is the purpose of page translation in the 80386 architecture?
Answer
Transforms a linear address into a physical address, implementing features for page-oriented virtual memory systems and page-level protection.
22
Question
What are the three components of the paging mechanism in the 80386?
Answer
Page Directory, Page Tables, Page Frame
23
Question
What is a page frame?
Answer
A 4K-byte unit of contiguous addresses of physical memory.
24
Question
What is a page table?
Answer
It is an array of 32-bit page specifiers, 4KB in size and contains at most 1K 32-bit entries.
25
Question
What is the Page Directory Base Register (PDBR) or CR3 used for?
Answer
It is a register that stores the physical address of the current page directory.
26
Question
What does the Page Frame Address in a Page Table Entry specify?
Answer
Specifies the physical starting address of a page. Because pages are located on 4K boundaries, the low-order 12 bits are always zero.
27
Question
What does the Present bit (P) indicate in a Page Table Entry?
Answer
Indicates whether a page table entry can be used in address translation. P=1 indicates that the entry can be used.
28
Question
What are the functions of Accessed and Dirty bits in page table entries?
Answer
A(Accessed) bit is set before any access to the page. D(Dirty) bit is set before a write operation to the page is carried out.
29
Question
Which bits in the page table entries are used for page-level protection?
Answer
User/Supervisor (U/S) and Read/Write (R/W) bits.
30
Question
What is the Translation Lookaside Buffer (TLB)?
Answer
An on-chip cache that stores the most recently used page-table data for efficient address translation.