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Processor Structure and Instruction Cycle
Highlights from Flashcard Set on Processor Structure and Instruction Execution
Key Vocabulary Extraction
Arithmetic and Logic Unit (ALU)
The component of the processor responsible for performing arithmetic (addition, subtraction, etc.) and logical (AND, OR, NOT, etc.) operations on data.
Condition Code Registers (Flags)
Special bits set by hardware to represent the outcome of operations like zero result, carry, overflow, or equality; used to influence program control flow.
Control Unit (CU)
Processor component that manages instruction execution by directing data flow and controlling the ALU operations.
Fetch Cycle
The part of the instruction cycle where the processor retrieves an instruction from memory for execution.
Instruction Cycle
The sequence of steps a processor follows to execute an instruction, generally including fetching, decoding, executing, and possibly interrupt handling.
Instruction Register (IR)
A register holding the currently fetched instruction ready for decoding.
Memory Address Register (MAR)
Stores the memory address of data or instructions to be fetched or written.
Memory Buffer Register (MBR)
Holds data that is either being written to or read from memory.
Pipeline (Instruction Pipeline)
Technique that breaks instruction execution into stages allowing multiple instructions to overlap in execution, thus improving throughput.
Program Counter (PC)
Holds the address of the next instruction to be fetched from memory.
Program Status Word (PSW)
A register or set of registers holding status flags and control bits indicating arithmetic results and processor operating modes.
Register
Small, fast storage locations inside the processor used to hold instructions, addresses, data, or status information.
Supervisor Mode
A privileged processor mode that allows execution of special instructions and access to restricted memory areas.
User-Visible Registers
Registers available for use by assembly language programmers, including general-purpose, data, address, and condition code registers.
2. Key Concepts Identification
Processor Components and Data Flow
The processor consists primarily of the ALU, Control Unit, and registers, interconnected by internal buses to facilitate data transfer and instruction execution.
Registers serve dual roles: internal control/status functions and visible registers for programming and optimization.
Register Types and Roles
Registers are categorized as:
General-purpose registers: versatile for various operations.
Data registers: store data values.
Address registers: hold memory addresses with specialized roles.
Condition code registers: track status of operations to guide decisions.
Instruction Execution Cycle
Divided into stages: Fetch, (optional) Indirect, Execute, and Interrupt.
Fetch stage: Retrieve the instruction from memory, using PC → MAR → Memory → MBR → IR steps.
Indirect stage: Fetch address or operand data if indirect addressing is used.
Interrupt stage: Save current PC, save state, then jump to interrupt service routine when interrupts are enabled and requested.
Instruction Pipelining
Instructions pass through multiple distinct stages, similar to an assembly line, enabling multiple instructions to be processed simultaneously at different stages.
Basic pipeline stages include Fetch and Execute, which can be further subdivided to improve throughput.
Pipeline performance depends on balancing stage delays and managing hazards such as branches causing pipeline stalls.
3. Important Data Highlighting
Pipeline Cycle Time Formula:
\[
\tau = \max(\tau_i) + d
\]
Where:
\(\tau\) = cycle time of the pipeline stage
\(\tau_i\) = delay of the \(i^{th}\) pipeline stage (from 1 to \(k\))
\(d\) = latch delay between pipeline stages
This formula gives the minimum clock period required in a pipelined processor considering the slowest stage plus the overhead of latching.
Major Control and Status Registers:
Program Counter (PC): holds next instruction address.
Instruction Register (IR): stores current instruction.
Memory Address Register (MAR): memory address for operand or instruction.
Memory Buffer Register (MBR): data read from or written to memory.
4. Additional Critical Aspects
Principle of Temporality in Registers:
Registers provide fast, temporary storage to facilitate efficient instruction processing and data manipulation.
Role of Condition Codes and Flags:
They allow decision-making in programs based on arithmetic results and help manage program control flow efficiently.
Supervisor vs. User Mode:
Protects system integrity by restricting privileged instructions and sensitive resources to supervisor mode only.
Methodology of Instruction Execution:
Fetch, Decode, Execute cycles form the core of processor operations.
Indirect cycles handle complex addressing modes ensuring flexibility.
Interrupt handling supports responsiveness by temporarily suspending program execution to handle external or internal events.
Instruction Pipeline Stages Detail:
Fetch Instruction (FI): Obtain instruction from memory.
Decode Instruction (DI): Determine operation and required operands.
Calculate Operands (CO): Compute effective addresses as needed.
Fetch Operands (FO): Retrieve operand data.
Execute Instruction (EI): Perform the operation.
Write Operand (WO): Store results to memory or registers.
Impact of Branch Instructions on Pipelines:
Conditional branches may cause the pipeline to stall or flush instructions in progress, decreasing pipeline efficiency due to uncertainty about control flow.
5. Summary Table: Processor Register Functions
| Register | Function |
|---------------------|------------------------------------------------------------------|
| Program Counter (PC) | Holds address of next instruction to fetch. |
| Instruction Register (IR) | Holds the instruction being decoded and executed. |
| Memory Address Register (MAR) | Stores address for memory access (read/write). |
| Memory Buffer Register (MBR) | Stores data read from or to be written to memory. |
| Condition Code Registers | Flags indicating status of arithmetic/logic operations. |
| Program Status Word (PSW) | Contains flags, interrupt enable bit, and mode indication. |
End of Highlights